Semiconductor Experts to Explore New Insulators

Conference covers new materials for integrated circuits

6 October 2009

Making transistors smaller is hitting a roadblock: The insulating layer in the devices can’t be made thinner. One way to get around the dilemma is to use other materials than ones usually based on silicon. But what are the best materials to use?

That is just one of the topics to be discussed at the IEEE Semiconductor Interface Specialists Conference (SISC), being held 3 to 5 December in Arlington, Va.

To help device engineers, materials scientists, and others get up to speed on the new materials, the conference is covering semiconductor/insulator interfaces, the physics of insulating thin films, and the interaction needed among the different fields of expertise. This year’s conference also explores novel technologies such as dielectrics on nanowires and on carbon-based channels, as well as oxide electronics.

“The insulator in the most advanced chip technologies is about 1 nanometer thick. A silicon oxide layer that is thinner is no longer an insulator,” says Martin Frank, the conference technical program chair.

“Transistors can be made smaller by moving away from silicon oxide to other insulators,” he continues. “Their fundamental properties must include a higher dielectric constant ‘k’ than silicon oxide, and therefore they are commonly referred to as ‘high-k dielectrics’.” Frank is a research staff member at the IBM Thomas J. Watson Research Center, in Yorktown Heights, N.Y., where he focuses on high-k dielectrics, metal gate electrodes, high-carrier-mobility materials, and ferroelectrics for CMOS transistor scaling.

In many of the 40 years the conference has been held, silicon and silicon oxide have been the main topics of discussion, and they continue to play important roles. But now other materials have taken center stage, including hafnium oxide-based compounds and new channel materials including germanium and indium gallium arsenide.

“For future transistors, researchers are moving away from conventional semiconductors to carbon-based channel materials such as carbon nanotubes and graphene,” Frank says. “These are long-term approaches that probably won’t appear in products until well into the next decade but are being discussed at this meeting.” Graphene is the basic structural element of many forms of carbon, including graphite, carbon nanotubes, and fullerenes.

Already being applied in some of today’s products are the hafnium oxide-based compounds that replace silicon oxide. Speakers are expected to discuss how the compounds’ properties change when mixed with other metal oxides, and what effects that has.

To make sense of it all, several leaders in the field have been invited to make presentations. Tso-Ping Ma, an electrical engineering professor at Yale University, is set to explore the evolution of gate dielectrics and their interfaces. Ma, who attended 30 previous sessions of the conference, also plans to speak—in recognition of this, the 40th gathering—about breakthroughs in dielectric technology that were first reported at SISC, and about how the event has changed over the years. Ma is co-director of the Yale Center for Microelectronic Materials and Structures.

Other scheduled speakers include Jan Van Houdt, memory group manager at IMEC in Leuven, Belgium, whose presentation is titled “Memory Technology: Evolutionary Versus Revolutionary Concepts”; and Naoto Umezawa, a researcher with the National Institute of Materials Science in Tsukuba, Japan, whose paper is on “Quality Control of High-k Gate Oxides by Doping With Impurities: Guidelines From Theory.”

SISC is sponsored by the IEEE Electron Devices Society and is held the week before the society’s main conference, the International Electron Devices Meeting, which is taking place from 7 to 9 December in Baltimore.

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